Initial commit
This commit is contained in:
谢洪龙
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S123D0852A0350BF45A68E5D2B0E3D452606A686BE462B044A582AFC5838444656BF45B73C
|
||||
S123D0A5448188F6B744E601B745E602B746E603B747848188B644F7B645E701B646E70234
|
||||
S123D0C5B647E70384813580004820023F485D2A095072100048721200484D2A05409012E1
|
||||
S123D0E500486237482A065F9724055081270150813580004B20023F4B905D2A0A905072C6
|
||||
S123D10510004B7212004B4D2A05409012004B9062374B2A09905F909724079050812702C1
|
||||
S107D1259050818021
|
||||
S12386AE000000000000000000000000000000000000000000000030000000000000000078
|
||||
S11D86CE4E00001E000500000000000000000000000000000000000000001D
|
||||
S12386E800000000000000000000000000000000000000000000000000000000000000006E
|
||||
S123870800000000000000000000000000000000000000000000000000000026E200000045
|
||||
S12087280000000000000000007777772E6966697368372E636F6D000000000000E6
|
||||
S1238000820087458200D1288200D1288200D1288200D1288200D1288200D1288200D128B1
|
||||
S12380208200D1288200D1288200D1288200D1288200D1288200D1288200D1288200D12864
|
||||
S12380408200D1288200D1288200D1288200D1288200D1288200D1288200CAFE8200CABEE6
|
||||
S12380608200D1288200CB228200D1288200D1288200D1288200D1288200D1288200D12830
|
||||
S11086A186AE62000086E864010087450093
|
||||
S903FFFFFE
|
||||
@@ -0,0 +1,5 @@
|
||||
/* STM8S005K6.h */
|
||||
#ifdef MCU_NAME
|
||||
#define STM8S005K6 1
|
||||
#endif
|
||||
#include "STM8S105K.h"
|
||||
@@ -0,0 +1,786 @@
|
||||
/* STM8S105K.h */
|
||||
|
||||
/* Copyright (c) 2003-2012 STMicroelectronics */
|
||||
|
||||
#ifndef __STM8S105K__
|
||||
#define __STM8S105K__
|
||||
|
||||
/* STM8S105K */
|
||||
|
||||
/* Check MCU name */
|
||||
#ifdef MCU_NAME
|
||||
#define STM8S105K 1
|
||||
#if (MCU_NAME != STM8S105K)
|
||||
#error "wrong include file STM8S105K.h for chosen MCU!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __CSMC__
|
||||
#define DEF_8BIT_REG_AT(NAME,ADDRESS) volatile unsigned char NAME @ADDRESS
|
||||
#define DEF_16BIT_REG_AT(NAME,ADDRESS) volatile unsigned int NAME @ADDRESS
|
||||
#endif
|
||||
|
||||
#ifdef __RAISONANCE__
|
||||
#define DEF_8BIT_REG_AT(NAME,ADDRESS) at ADDRESS hreg NAME
|
||||
#define DEF_16BIT_REG_AT(NAME,ADDRESS) at ADDRESS hreg16 NAME
|
||||
#endif
|
||||
|
||||
/* Port A */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port A data output latch register */
|
||||
DEF_8BIT_REG_AT(PA_ODR,0x5000);
|
||||
|
||||
/* Port A input pin value register */
|
||||
DEF_8BIT_REG_AT(PA_IDR,0x5001);
|
||||
|
||||
/* Port A data direction register */
|
||||
DEF_8BIT_REG_AT(PA_DDR,0x5002);
|
||||
|
||||
/* Port A control register 1 */
|
||||
DEF_8BIT_REG_AT(PA_CR1,0x5003);
|
||||
|
||||
/* Port A control register 2 */
|
||||
DEF_8BIT_REG_AT(PA_CR2,0x5004);
|
||||
|
||||
/* Port B */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port B data output latch register */
|
||||
DEF_8BIT_REG_AT(PB_ODR,0x5005);
|
||||
|
||||
/* Port B input pin value register */
|
||||
DEF_8BIT_REG_AT(PB_IDR,0x5006);
|
||||
|
||||
/* Port B data direction register */
|
||||
DEF_8BIT_REG_AT(PB_DDR,0x5007);
|
||||
|
||||
/* Port B control register 1 */
|
||||
DEF_8BIT_REG_AT(PB_CR1,0x5008);
|
||||
|
||||
/* Port B control register 2 */
|
||||
DEF_8BIT_REG_AT(PB_CR2,0x5009);
|
||||
|
||||
/* Port C */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port C data output latch register */
|
||||
DEF_8BIT_REG_AT(PC_ODR,0x500a);
|
||||
|
||||
/* Port C input pin value register */
|
||||
DEF_8BIT_REG_AT(PC_IDR,0x500b);
|
||||
|
||||
/* Port C data direction register */
|
||||
DEF_8BIT_REG_AT(PC_DDR,0x500c);
|
||||
|
||||
/* Port C control register 1 */
|
||||
DEF_8BIT_REG_AT(PC_CR1,0x500d);
|
||||
|
||||
/* Port C control register 2 */
|
||||
DEF_8BIT_REG_AT(PC_CR2,0x500e);
|
||||
|
||||
/* Port D */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port D data output latch register */
|
||||
DEF_8BIT_REG_AT(PD_ODR,0x500f);
|
||||
|
||||
/* Port D input pin value register */
|
||||
DEF_8BIT_REG_AT(PD_IDR,0x5010);
|
||||
|
||||
/* Port D data direction register */
|
||||
DEF_8BIT_REG_AT(PD_DDR,0x5011);
|
||||
|
||||
/* Port D control register 1 */
|
||||
DEF_8BIT_REG_AT(PD_CR1,0x5012);
|
||||
|
||||
/* Port D control register 2 */
|
||||
DEF_8BIT_REG_AT(PD_CR2,0x5013);
|
||||
|
||||
/* Port E */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port E data output latch register */
|
||||
DEF_8BIT_REG_AT(PE_ODR,0x5014);
|
||||
|
||||
/* Port E input pin value register */
|
||||
DEF_8BIT_REG_AT(PE_IDR,0x5015);
|
||||
|
||||
/* Port E data direction register */
|
||||
DEF_8BIT_REG_AT(PE_DDR,0x5016);
|
||||
|
||||
/* Port E control register 1 */
|
||||
DEF_8BIT_REG_AT(PE_CR1,0x5017);
|
||||
|
||||
/* Port E control register 2 */
|
||||
DEF_8BIT_REG_AT(PE_CR2,0x5018);
|
||||
|
||||
/* Port F */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port F data output latch register */
|
||||
DEF_8BIT_REG_AT(PF_ODR,0x5019);
|
||||
|
||||
/* Port F input pin value register */
|
||||
DEF_8BIT_REG_AT(PF_IDR,0x501a);
|
||||
|
||||
/* Port F data direction register */
|
||||
DEF_8BIT_REG_AT(PF_DDR,0x501b);
|
||||
|
||||
/* Port F control register 1 */
|
||||
DEF_8BIT_REG_AT(PF_CR1,0x501c);
|
||||
|
||||
/* Port F control register 2 */
|
||||
DEF_8BIT_REG_AT(PF_CR2,0x501d);
|
||||
|
||||
/* Flash */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Flash control register 1 */
|
||||
DEF_8BIT_REG_AT(FLASH_CR1,0x505a);
|
||||
|
||||
/* Flash control register 2 */
|
||||
DEF_8BIT_REG_AT(FLASH_CR2,0x505b);
|
||||
|
||||
/* Flash complementary control register 2 */
|
||||
DEF_8BIT_REG_AT(FLASH_NCR2,0x505c);
|
||||
|
||||
/* Flash protection register */
|
||||
DEF_8BIT_REG_AT(FLASH_FPR,0x505d);
|
||||
|
||||
/* Flash complementary protection register */
|
||||
DEF_8BIT_REG_AT(FLASH_NFPR,0x505e);
|
||||
|
||||
/* Flash in-application programming status register */
|
||||
DEF_8BIT_REG_AT(FLASH_IAPSR,0x505f);
|
||||
|
||||
/* Flash Program memory unprotection register */
|
||||
DEF_8BIT_REG_AT(FLASH_PUKR,0x5062);
|
||||
|
||||
/* Data EEPROM unprotection register */
|
||||
DEF_8BIT_REG_AT(FLASH_DUKR,0x5064);
|
||||
|
||||
/* External Interrupt Control Register (ITC) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* External interrupt control register 1 */
|
||||
DEF_8BIT_REG_AT(EXTI_CR1,0x50a0);
|
||||
|
||||
/* External interrupt control register 2 */
|
||||
DEF_8BIT_REG_AT(EXTI_CR2,0x50a1);
|
||||
|
||||
/* Reset (RST) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Reset status register 1 */
|
||||
DEF_8BIT_REG_AT(RST_SR,0x50b3);
|
||||
|
||||
/* Clock Control (CLK) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Internal clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_ICKR,0x50c0);
|
||||
|
||||
/* External clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_ECKR,0x50c1);
|
||||
|
||||
/* Clock master status register */
|
||||
DEF_8BIT_REG_AT(CLK_CMSR,0x50c3);
|
||||
|
||||
/* Clock master switch register */
|
||||
DEF_8BIT_REG_AT(CLK_SWR,0x50c4);
|
||||
|
||||
/* Clock switch control register */
|
||||
DEF_8BIT_REG_AT(CLK_SWCR,0x50c5);
|
||||
|
||||
/* Clock divider register */
|
||||
DEF_8BIT_REG_AT(CLK_CKDIVR,0x50c6);
|
||||
|
||||
/* Peripheral clock gating register 1 */
|
||||
DEF_8BIT_REG_AT(CLK_PCKENR1,0x50c7);
|
||||
|
||||
/* Clock security system register */
|
||||
DEF_8BIT_REG_AT(CLK_CSSR,0x50c8);
|
||||
|
||||
/* Configurable clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_CCOR,0x50c9);
|
||||
|
||||
/* Peripheral clock gating register 2 */
|
||||
DEF_8BIT_REG_AT(CLK_PCKENR2,0x50ca);
|
||||
|
||||
/* CAN clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_CANCCR,0x50cb);
|
||||
|
||||
/* HSI clock calibration trimming register */
|
||||
DEF_8BIT_REG_AT(CLK_HSITRIMR,0x50cc);
|
||||
|
||||
/* SWIM clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_SWIMCCR,0x50cd);
|
||||
|
||||
/* Window Watchdog (WWDG) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* WWDG Control Register */
|
||||
DEF_8BIT_REG_AT(WWDG_CR,0x50d1);
|
||||
|
||||
/* WWDR Window Register */
|
||||
DEF_8BIT_REG_AT(WWDG_WR,0x50d2);
|
||||
|
||||
/* Independent Watchdog (IWDG) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* IWDG Key Register */
|
||||
DEF_8BIT_REG_AT(IWDG_KR,0x50e0);
|
||||
|
||||
/* IWDG Prescaler Register */
|
||||
DEF_8BIT_REG_AT(IWDG_PR,0x50e1);
|
||||
|
||||
/* IWDG Reload Register */
|
||||
DEF_8BIT_REG_AT(IWDG_RLR,0x50e2);
|
||||
|
||||
/* Auto Wake-Up (AWU) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* AWU Control/Status Register */
|
||||
DEF_8BIT_REG_AT(AWU_CSR,0x50f0);
|
||||
|
||||
/* AWU asynchronous prescaler buffer register */
|
||||
DEF_8BIT_REG_AT(AWU_APR,0x50f1);
|
||||
|
||||
/* AWU Timebase selection register */
|
||||
DEF_8BIT_REG_AT(AWU_TBR,0x50f2);
|
||||
|
||||
/* Beeper (BEEP) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* BEEP Control/Status Register */
|
||||
DEF_8BIT_REG_AT(BEEP_CSR,0x50f3);
|
||||
|
||||
/* Serial Peripheral Interface (SPI) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
DEF_8BIT_REG_AT(SPI_CR1,0x5200);
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
DEF_8BIT_REG_AT(SPI_CR2,0x5201);
|
||||
|
||||
/* SPI Interrupt Control Register */
|
||||
DEF_8BIT_REG_AT(SPI_ICR,0x5202);
|
||||
|
||||
/* SPI Status Register */
|
||||
DEF_8BIT_REG_AT(SPI_SR,0x5203);
|
||||
|
||||
/* SPI Data Register */
|
||||
DEF_8BIT_REG_AT(SPI_DR,0x5204);
|
||||
|
||||
/* SPI CRC Polynomial Register */
|
||||
DEF_8BIT_REG_AT(SPI_CRCPR,0x5205);
|
||||
|
||||
/* SPI Rx CRC Register */
|
||||
DEF_8BIT_REG_AT(SPI_RXCRCR,0x5206);
|
||||
|
||||
/* SPI Tx CRC Register */
|
||||
DEF_8BIT_REG_AT(SPI_TXCRCR,0x5207);
|
||||
|
||||
/* I2C Bus Interface (I2C) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* I2C control register 1 */
|
||||
DEF_8BIT_REG_AT(I2C_CR1,0x5210);
|
||||
|
||||
/* I2C control register 2 */
|
||||
DEF_8BIT_REG_AT(I2C_CR2,0x5211);
|
||||
|
||||
/* I2C frequency register */
|
||||
DEF_8BIT_REG_AT(I2C_FREQR,0x5212);
|
||||
|
||||
/* I2C Own address register low */
|
||||
DEF_8BIT_REG_AT(I2C_OARL,0x5213);
|
||||
|
||||
/* I2C Own address register high */
|
||||
DEF_8BIT_REG_AT(I2C_OARH,0x5214);
|
||||
|
||||
/* I2C data register */
|
||||
DEF_8BIT_REG_AT(I2C_DR,0x5216);
|
||||
|
||||
/* I2C status register 1 */
|
||||
DEF_8BIT_REG_AT(I2C_SR1,0x5217);
|
||||
|
||||
/* I2C status register 2 */
|
||||
DEF_8BIT_REG_AT(I2C_SR2,0x5218);
|
||||
|
||||
/* I2C status register 3 */
|
||||
DEF_8BIT_REG_AT(I2C_SR3,0x5219);
|
||||
|
||||
/* I2C interrupt control register */
|
||||
DEF_8BIT_REG_AT(I2C_ITR,0x521a);
|
||||
|
||||
/* I2C Clock control register low */
|
||||
DEF_8BIT_REG_AT(I2C_CCRL,0x521b);
|
||||
|
||||
/* I2C Clock control register high */
|
||||
DEF_8BIT_REG_AT(I2C_CCRH,0x521c);
|
||||
|
||||
/* I2C TRISE register */
|
||||
DEF_8BIT_REG_AT(I2C_TRISER,0x521d);
|
||||
|
||||
/* I2C packet error checking register */
|
||||
DEF_8BIT_REG_AT(I2C_PECR,0x521e);
|
||||
|
||||
/* LIN Universal asynch. receiver transmitter (UART2) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* UART2 Status Register */
|
||||
DEF_8BIT_REG_AT(UART2_SR,0x5240);
|
||||
|
||||
/* UART2 Data Register */
|
||||
DEF_8BIT_REG_AT(UART2_DR,0x5241);
|
||||
|
||||
/* UART2 Baud Rate Register 1 */
|
||||
DEF_8BIT_REG_AT(UART2_BRR1,0x5242);
|
||||
|
||||
/* UART2 Baud Rate Register 2 */
|
||||
DEF_8BIT_REG_AT(UART2_BRR2,0x5243);
|
||||
|
||||
/* UART2 Control Register 1 */
|
||||
DEF_8BIT_REG_AT(UART2_CR1,0x5244);
|
||||
|
||||
/* UART2 Control Register 2 */
|
||||
DEF_8BIT_REG_AT(UART2_CR2,0x5245);
|
||||
|
||||
/* UART2 Control Register 3 */
|
||||
DEF_8BIT_REG_AT(UART2_CR3,0x5246);
|
||||
|
||||
/* UART2 Control Register 4 */
|
||||
DEF_8BIT_REG_AT(UART2_CR4,0x5247);
|
||||
|
||||
/* UART2 Control Register 5 */
|
||||
DEF_8BIT_REG_AT(UART2_CR5,0x5248);
|
||||
|
||||
/* UART2 Control Register 6 */
|
||||
DEF_8BIT_REG_AT(UART2_CR6,0x5249);
|
||||
|
||||
/* UART2 Guard time Register */
|
||||
DEF_8BIT_REG_AT(UART2_GTR,0x524a);
|
||||
|
||||
/* UART2 Prescaler Register */
|
||||
DEF_8BIT_REG_AT(UART2_PSCR,0x524b);
|
||||
|
||||
/* 16-Bit Timer 1 (TIM1) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM1 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_CR1,0x5250);
|
||||
|
||||
/* TIM1 Control register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_CR2,0x5251);
|
||||
|
||||
/* TIM1 Slave Mode Control register */
|
||||
DEF_8BIT_REG_AT(TIM1_SMCR,0x5252);
|
||||
|
||||
/* TIM1 external trigger register */
|
||||
DEF_8BIT_REG_AT(TIM1_ETR,0x5253);
|
||||
|
||||
/* TIM1 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM1_IER,0x5254);
|
||||
|
||||
/* TIM1 Status register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_SR1,0x5255);
|
||||
|
||||
/* TIM1 Status register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_SR2,0x5256);
|
||||
|
||||
/* TIM1 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM1_EGR,0x5257);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR1,0x5258);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR2,0x5259);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 3 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR3,0x525a);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 4 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR4,0x525b);
|
||||
|
||||
/* TIM1 Capture/Compare enable register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCER1,0x525c);
|
||||
|
||||
/* TIM1 Capture/Compare enable register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCER2,0x525d);
|
||||
|
||||
/* TIM1 Counter */
|
||||
DEF_16BIT_REG_AT(TIM1_CNTR,0x525e);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CNTRH,0x525e);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CNTRL,0x525f);
|
||||
|
||||
/* TIM1 Prescaler register */
|
||||
DEF_16BIT_REG_AT(TIM1_PSCR,0x5260);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_PSCRH,0x5260);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_PSCRL,0x5261);
|
||||
|
||||
/* TIM1 Auto-reload register */
|
||||
DEF_16BIT_REG_AT(TIM1_ARR,0x5262);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_ARRH,0x5262);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_ARRL,0x5263);
|
||||
|
||||
/* TIM1 Repetition counter register */
|
||||
DEF_8BIT_REG_AT(TIM1_RCR,0x5264);
|
||||
|
||||
/* TIM1 Capture/Compare register 1 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR1,0x5265);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR1H,0x5265);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR1L,0x5266);
|
||||
|
||||
/* TIM1 Capture/Compare register 2 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR2,0x5267);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR2H,0x5267);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR2L,0x5268);
|
||||
|
||||
/* TIM1 Capture/Compare register 3 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR3,0x5269);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR3H,0x5269);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR3L,0x526a);
|
||||
|
||||
/* TIM1 Capture/Compare register 4 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR4,0x526b);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR4H,0x526b);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR4L,0x526c);
|
||||
|
||||
/* TIM1 Break register */
|
||||
DEF_8BIT_REG_AT(TIM1_BKR,0x526d);
|
||||
|
||||
/* TIM1 Dead-time register */
|
||||
DEF_8BIT_REG_AT(TIM1_DTR,0x526e);
|
||||
|
||||
/* TIM1 Output idle state register */
|
||||
DEF_8BIT_REG_AT(TIM1_OISR,0x526f);
|
||||
|
||||
/* 16-Bit Timer 2 (TIM2) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM2 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_CR1,0x5300);
|
||||
|
||||
/* TIM2 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM2_IER,0x5301);
|
||||
|
||||
/* TIM2 Status register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_SR1,0x5302);
|
||||
|
||||
/* TIM2 Status register 2 */
|
||||
DEF_8BIT_REG_AT(TIM2_SR2,0x5303);
|
||||
|
||||
/* TIM2 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM2_EGR,0x5304);
|
||||
|
||||
/* TIM2 Capture/Compare mode register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCMR1,0x5305);
|
||||
|
||||
/* TIM2 Capture/Compare mode register 2 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCMR2,0x5306);
|
||||
|
||||
/* TIM2 Capture/Compare mode register 3 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCMR3,0x5307);
|
||||
|
||||
/* TIM2 Capture/Compare enable register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCER1,0x5308);
|
||||
|
||||
/* TIM2 Capture/Compare enable register 2 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCER2,0x5309);
|
||||
|
||||
/* TIM2 Counter */
|
||||
DEF_16BIT_REG_AT(TIM2_CNTR,0x530a);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CNTRH,0x530a);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CNTRL,0x530b);
|
||||
|
||||
/* TIM2 Prescaler register */
|
||||
DEF_8BIT_REG_AT(TIM2_PSCR,0x530c);
|
||||
|
||||
/* TIM2 Auto-reload register */
|
||||
DEF_16BIT_REG_AT(TIM2_ARR,0x530d);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_ARRH,0x530d);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_ARRL,0x530e);
|
||||
|
||||
/* TIM2 Capture/Compare register 1 */
|
||||
DEF_16BIT_REG_AT(TIM2_CCR1,0x530f);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR1H,0x530f);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR1L,0x5310);
|
||||
|
||||
/* TIM2 Capture/Compare register 2 */
|
||||
DEF_16BIT_REG_AT(TIM2_CCR2,0x5311);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR2H,0x5311);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR2L,0x5312);
|
||||
|
||||
/* TIM2 Capture/Compare register 3 */
|
||||
DEF_16BIT_REG_AT(TIM2_CCR3,0x5313);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR3H,0x5313);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR3L,0x5314);
|
||||
|
||||
/* 16-Bit Timer 3 (TIM3) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM3 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_CR1,0x5320);
|
||||
|
||||
/* TIM3 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM3_IER,0x5321);
|
||||
|
||||
/* TIM3 Status register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_SR1,0x5322);
|
||||
|
||||
/* TIM3 Status register 2 */
|
||||
DEF_8BIT_REG_AT(TIM3_SR2,0x5323);
|
||||
|
||||
/* TIM3 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM3_EGR,0x5324);
|
||||
|
||||
/* TIM3 Capture/Compare mode register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_CCMR1,0x5325);
|
||||
|
||||
/* TIM3 Capture/Compare mode register 2 */
|
||||
DEF_8BIT_REG_AT(TIM3_CCMR2,0x5326);
|
||||
|
||||
/* TIM3 Capture/Compare enable register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_CCER1,0x5327);
|
||||
|
||||
/* TIM3 Counter */
|
||||
DEF_16BIT_REG_AT(TIM3_CNTR,0x5328);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_CNTRH,0x5328);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_CNTRL,0x5329);
|
||||
|
||||
/* TIM3 Prescaler register */
|
||||
DEF_8BIT_REG_AT(TIM3_PSCR,0x532a);
|
||||
|
||||
/* TIM3 Auto-reload register */
|
||||
DEF_16BIT_REG_AT(TIM3_ARR,0x532b);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_ARRH,0x532b);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_ARRL,0x532c);
|
||||
|
||||
/* TIM3 Capture/Compare register */
|
||||
DEF_16BIT_REG_AT(TIM3_CCR1,0x532d);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR1H,0x532d);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR1L,0x532e);
|
||||
|
||||
/* TIM3 Capture/Compare register */
|
||||
DEF_16BIT_REG_AT(TIM3_CCR2,0x532f);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR2H,0x532f);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR2L,0x5330);
|
||||
|
||||
/* 8-Bit Timer 4 (TIM4) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM4 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM4_CR1,0x5340);
|
||||
|
||||
/* TIM4 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM4_IER,0x5341);
|
||||
|
||||
/* TIM4 Status register */
|
||||
DEF_8BIT_REG_AT(TIM4_SR,0x5342);
|
||||
|
||||
/* TIM4 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM4_EGR,0x5343);
|
||||
|
||||
/* TIM4 Counter */
|
||||
DEF_8BIT_REG_AT(TIM4_CNTR,0x5344);
|
||||
|
||||
/* TIM4 Prescaler register */
|
||||
DEF_8BIT_REG_AT(TIM4_PSCR,0x5345);
|
||||
|
||||
/* TIM4 Auto-reload register */
|
||||
DEF_8BIT_REG_AT(TIM4_ARR,0x5346);
|
||||
|
||||
/* 10-Bit A/D Converter (ADC1) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* ADC Data buffer Register 0 */
|
||||
DEF_16BIT_REG_AT(ADC_DB0R,0x53e0);
|
||||
/* Data Buffer register 0 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB0RH,0x53e0);
|
||||
/* Data Buffer register 0 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB0RL,0x53e1);
|
||||
|
||||
/* ADC Data buffer Register 1 */
|
||||
DEF_16BIT_REG_AT(ADC_DB1R,0x53e2);
|
||||
/* Data Buffer register 1 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB1RH,0x53e2);
|
||||
/* Data Buffer register 1 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB1RL,0x53e3);
|
||||
|
||||
/* ADC Data buffer Register 2 */
|
||||
DEF_16BIT_REG_AT(ADC_DB2R,0x53e4);
|
||||
/* Data Buffer register 2 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB2RH,0x53e4);
|
||||
/* Data Buffer register 2 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB2RL,0x53e5);
|
||||
|
||||
/* ADC Data buffer Register 3 */
|
||||
DEF_16BIT_REG_AT(ADC_DB3R,0x53e6);
|
||||
/* Data Buffer register 3 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB3RH,0x53e6);
|
||||
/* Data Buffer register 3 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB3RL,0x53e7);
|
||||
|
||||
/* ADC Data buffer Register 4 */
|
||||
DEF_16BIT_REG_AT(ADC_DB4R,0x53e8);
|
||||
/* Data Buffer register 4 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB4RH,0x53e8);
|
||||
/* Data Buffer register 4 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB4RL,0x53e9);
|
||||
|
||||
/* ADC Data buffer Register 5 */
|
||||
DEF_16BIT_REG_AT(ADC_DB5R,0x53ea);
|
||||
/* Data Buffer register 5 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB5RH,0x53ea);
|
||||
/* Data Buffer register 5 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB5RL,0x53eb);
|
||||
|
||||
/* ADC Data buffer Register 6 */
|
||||
DEF_16BIT_REG_AT(ADC_DB6R,0x53ec);
|
||||
/* Data Buffer register 6 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB6RH,0x53ec);
|
||||
/* Data Buffer register 6 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB6RL,0x53ed);
|
||||
|
||||
/* ADC Data buffer Register 7 */
|
||||
DEF_16BIT_REG_AT(ADC_DB7R,0x53ee);
|
||||
/* Data Buffer register 7 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB7RH,0x53ee);
|
||||
/* Data Buffer register 7 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB7RL,0x53ef);
|
||||
|
||||
/* ADC Data buffer Register 8 */
|
||||
DEF_16BIT_REG_AT(ADC_DB8R,0x53f0);
|
||||
/* Data Buffer register 8 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB8RH,0x53f0);
|
||||
/* Data Buffer register 8 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB8RL,0x53f1);
|
||||
|
||||
/* ADC Data buffer Register 9 */
|
||||
DEF_16BIT_REG_AT(ADC_DB9R,0x53f2);
|
||||
/* Data Buffer register 9 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB9RH,0x53f2);
|
||||
/* Data Buffer register 9 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB9RL,0x53f3);
|
||||
|
||||
/* ADC Control/Status Register */
|
||||
DEF_8BIT_REG_AT(ADC_CSR,0x5400);
|
||||
|
||||
/* ADC Configuration Register 1 */
|
||||
DEF_8BIT_REG_AT(ADC_CR1,0x5401);
|
||||
|
||||
/* ADC Configuration Register 2 */
|
||||
DEF_8BIT_REG_AT(ADC_CR2,0x5402);
|
||||
|
||||
/* ADC Configuration Register 3 */
|
||||
DEF_8BIT_REG_AT(ADC_CR3,0x5403);
|
||||
|
||||
/* ADC Data Register */
|
||||
DEF_16BIT_REG_AT(ADC_DR,0x5404);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(ADC_DRH,0x5404);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(ADC_DRL,0x5405);
|
||||
|
||||
/* ADC Schmitt Trigger Disable Register */
|
||||
DEF_16BIT_REG_AT(ADC_TDR,0x5406);
|
||||
/* Schmitt trigger disable High */
|
||||
DEF_8BIT_REG_AT(ADC_TDRH,0x5406);
|
||||
/* Schmitt trigger disable Low */
|
||||
DEF_8BIT_REG_AT(ADC_TDRL,0x5407);
|
||||
|
||||
/* ADC High Threshold Register */
|
||||
DEF_16BIT_REG_AT(ADC_HTR,0x5408);
|
||||
/* High Threshold Register High */
|
||||
DEF_8BIT_REG_AT(ADC_HTRH,0x5408);
|
||||
/* High Threshold Register Low */
|
||||
DEF_8BIT_REG_AT(ADC_HTRL,0x5409);
|
||||
|
||||
/* ADC Low Threshold Register */
|
||||
DEF_16BIT_REG_AT(ADC_LTR,0x540a);
|
||||
/* Low Threshold Register High */
|
||||
DEF_8BIT_REG_AT(ADC_LTRH,0x540a);
|
||||
/* Low Threshold Register Low */
|
||||
DEF_8BIT_REG_AT(ADC_LTRL,0x540b);
|
||||
|
||||
/* ADC Analog Watchdog Status Register */
|
||||
DEF_16BIT_REG_AT(ADC_AWSR,0x540c);
|
||||
/* Analog Watchdog Status register High */
|
||||
DEF_8BIT_REG_AT(ADC_AWSRH,0x540c);
|
||||
/* Analog Watchdog Status register Low */
|
||||
DEF_8BIT_REG_AT(ADC_AWSRL,0x540d);
|
||||
|
||||
/* ADC Analog Watchdog Control Register */
|
||||
DEF_16BIT_REG_AT(ADC_AWCR,0x540e);
|
||||
/* Analog Watchdog Control register High */
|
||||
DEF_8BIT_REG_AT(ADC_AWCRH,0x540e);
|
||||
/* Analog Watchdog Control register Low */
|
||||
DEF_8BIT_REG_AT(ADC_AWCRL,0x540f);
|
||||
|
||||
/* Global configuration register (CFG) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* CFG Global configuration register */
|
||||
DEF_8BIT_REG_AT(CFG_GCR,0x7f60);
|
||||
|
||||
/* Interrupt Software Priority Register (ITC) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Interrupt Software priority register 1 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR1,0x7f70);
|
||||
|
||||
/* Interrupt Software priority register 2 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR2,0x7f71);
|
||||
|
||||
/* Interrupt Software priority register 3 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR3,0x7f72);
|
||||
|
||||
/* Interrupt Software priority register 4 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR4,0x7f73);
|
||||
|
||||
/* Interrupt Software priority register 5 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR5,0x7f74);
|
||||
|
||||
/* Interrupt Software priority register 6 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR6,0x7f75);
|
||||
|
||||
/* Interrupt Software priority register 7 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR7,0x7f76);
|
||||
|
||||
#endif /* __STM8S105K__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,63 @@
|
||||
/* BASIC INTERRUPT VECTOR TABLE FOR STM8 devices
|
||||
* Copyright (c) 2007 STMicroelectronics
|
||||
*/
|
||||
|
||||
typedef void @far (*interrupt_handler_t)(void);
|
||||
|
||||
struct interrupt_vector {
|
||||
unsigned char interrupt_instruction;
|
||||
interrupt_handler_t interrupt_handler;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
@far @interrupt void NonHandledInterrupt (void)
|
||||
{
|
||||
// in order to detect unexpected events during development,
|
||||
// it is recommended to set a breakpoint on the following instruction
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void _stext(); /* startup routine */
|
||||
extern @far @interrupt void TIM4_UPD_OVF_IRQHandler (void);
|
||||
extern @far @interrupt void UART2_Send_IRQHandler (void);
|
||||
extern @far @interrupt void UART2_Recv_IRQHandler (void);
|
||||
|
||||
struct interrupt_vector const _vectab[] = {
|
||||
{0x82, (interrupt_handler_t)_stext}, /* reset */
|
||||
{0x82, NonHandledInterrupt}, /* trap */
|
||||
{0x82, NonHandledInterrupt}, /* irq0 */
|
||||
{0x82, NonHandledInterrupt}, /* irq1 */
|
||||
{0x82, NonHandledInterrupt}, /* irq2 */
|
||||
{0x82, NonHandledInterrupt}, /* irq3 */
|
||||
{0x82, NonHandledInterrupt}, /* irq4 */
|
||||
{0x82, NonHandledInterrupt}, /* irq5 */
|
||||
{0x82, NonHandledInterrupt}, /* irq6 */
|
||||
{0x82, NonHandledInterrupt}, /* irq7 */
|
||||
{0x82, NonHandledInterrupt}, /* irq8 */
|
||||
{0x82, NonHandledInterrupt}, /* irq9 */
|
||||
{0x82, NonHandledInterrupt}, /* irq10 */
|
||||
{0x82, NonHandledInterrupt}, /* irq11 */
|
||||
{0x82, NonHandledInterrupt}, /* irq12 */
|
||||
{0x82, NonHandledInterrupt}, /* irq13 */
|
||||
{0x82, NonHandledInterrupt}, /* irq14 */
|
||||
{0x82, NonHandledInterrupt}, /* irq15 */
|
||||
{0x82, NonHandledInterrupt}, /* irq16 */
|
||||
{0x82, NonHandledInterrupt}, /* irq17 */
|
||||
{0x82, NonHandledInterrupt}, /* irq18 */
|
||||
{0x82, NonHandledInterrupt}, /* irq19 */
|
||||
{0x82, UART2_Send_IRQHandler}, /* irq20 UART2/3·¢ËÍÖжÏ*/
|
||||
{0x82, UART2_Recv_IRQHandler}, /* irq21 UART2/3½ÓÊÕÖжÏ*/
|
||||
{0x82, NonHandledInterrupt}, /* irq22 */
|
||||
{0x82, TIM4_UPD_OVF_IRQHandler}, /* irq23 */
|
||||
{0x82, NonHandledInterrupt}, /* irq24 */
|
||||
{0x82, NonHandledInterrupt}, /* irq25 */
|
||||
{0x82, NonHandledInterrupt}, /* irq26 */
|
||||
{0x82, NonHandledInterrupt}, /* irq27 */
|
||||
{0x82, NonHandledInterrupt}, /* irq28 */
|
||||
{0x82, NonHandledInterrupt}, /* irq29 */
|
||||
};
|
||||
@@ -0,0 +1,693 @@
|
||||
S016000044656275675C332D636F6E74726F6C2E736D38FF
|
||||
S1238080312C22554450222C223139322E3136382E302E313034222C333333302C2254437E
|
||||
S12380A050222C223132302E35352E3139302E3536222C39393535312C22554450222C226E
|
||||
S12380C03132302E35352E3139302E3536222C33333341542B52535441542B524553544F23
|
||||
S12380E0524541542B43575354415254534D4152543D3341542B43574D4F44453D41542B8A
|
||||
S12381004349504D4F44453D41542B4349504D55583D41542B434946535241542B43495077
|
||||
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S123D13B0800830024257206008100241E720A00820024175FBF04BE061C0001BF06A3011C
|
||||
S123D15B9125325FBF06CDA0F1202A720800830025237206008100241C720A008200241547
|
||||
S123D17B5FBF06BE041C0001BF04A3019125065FBF04CDA0F1720C00860024103C0DB60DA6
|
||||
S123D19BA15B25083C353F0D721E0086720C00860025023F0D7206008600240D3C0CB60CC4
|
||||
S123D1BBA15B25053F0CCDA0F1720200810024023F0C720E0084002415720E008100240EAB
|
||||
S123D1DB3C12B612A12325063F1272160084720E00840025023F1272080085002415BE0A52
|
||||
S123D1FB1C0001BF0AA303E9250C5FBF0A7214008420035FBF0A720800820024173C27B69D
|
||||
S123D21B27A10B250F3F2772190082721600824529283F2985BF4B32004D85BF4832004A57
|
||||
S123D23B80BF485A5C7D26FC72B000488189520420261F011E091F03F626041E05201F1EDA
|
||||
S123D25B01F61E03F127071E055C1F05200A1E015C1F011E035C20DE1E05F626D55F5B06C1
|
||||
S123D27B81E60388E60288E60188F626040D01270EA880200AE60388E60288E60188F6883B
|
||||
S123D29B1A02270BBE44260A85BF4485BF46815B048190893F495839499EB7481E035839B2
|
||||
S123D2BB499E5FB048271F972228A1E9251E409716057B04AA804490565A26FA6B04170553
|
||||
S123D2DB721E0045202C721E00452020206B908520B6A11824F8BB48B74890BE46B645AA73
|
||||
S123D2FB804490565A26FAB74590BF467B04AA806B04BE46B64534492204241E261C72F0BA
|
||||
S123D31B05120424073349435026014C4D2B1E26165D2613BF46BF44201F72FB05190424C4
|
||||
S123D33B0C46563C4820063A4858492AFABF464897B64895344956BF4490855B0481B644F9
|
||||
S123D35BF4B749B644F82A05F82B1B201DB644F0261AB645E101260CB646E1022606B647DD
|
||||
S123D37BE103270E2404A6FF2002A601720F004901409C81B644BA452711E60388E60288A5
|
||||
S123D39BE60188F6881A0226035B048190897B03720F004404A8806B03AA80080449B748E8
|
||||
S123D3BB0604B645721E004548B64449B048AB7FB7443518004907030803B645BE4690583A
|
||||
S123D3DB39480703250A1104250D22041305250772F0051204905C584909033A4926DFB66F
|
||||
S123D3FB482B059058493A44480803364446B74590BF4690855B048189CDD29085CCD5B3BD
|
||||
S123D41BB644BA452712E60388E60288FE891E012607BF44BF465B04817B01720F004404DA
|
||||
S123D43BA8806B01AA800802490602A07EB748B645721E004548B64449BB48B7447B02BE03
|
||||
S123D45B4442BF487B03BE44423F4AAD5E7B04BE44429FAD647B02BE4542AD4F7B03BE4518
|
||||
S123D47B42AD537B04BE45423F46AD5C7B02BE4642AD437B03BE4642AD4E7B04BE46429E24
|
||||
S123D49BBB4624063C452602AD46BE49B6482B06384559493A444808013644463845B74549
|
||||
S123D4BBBF462404721000475B048172BB0049BF4924023C48819FBB45B7459EB94AB74A91
|
||||
S123D4DB24F3BE485CBF488172BB0045BF4524E53C4A27EE81CDD4F6BE468189BE4427556E
|
||||
S123D4FB4F5802A07F2A075FBF44BF4620479089A1372AF3565E90BE46A01727272A14406D
|
||||
S123D51BA1102B0790935FA01027195490564A26FA2011A1102B0793905FA0102706905898
|
||||
S123D53B594A26FA3D442A0653905026015C90BF46BF449085858188BF49909F5E42BF4889
|
||||
S123D55BBE49909E4272BB0048BF48BE49909F423F4A72BB004984813F47BF4526033F4407
|
||||
S123D57B814545442A0350BF45A68E5D2B0E3D452606A686BE462B044A582AFC5838444603
|
||||
S123D59B56BF45B7448188F6B744E601B745E602B746E603B747848188B644F7B645E7010D
|
||||
S123D5BBB646E702B647E70384813580004820023F485D2A095072100048721200484D2AE8
|
||||
S123D5DB0540901200486237482A065F9724055081270150813580004B20023F4B905D2A40
|
||||
S123D5FB0A90507210004B7212004B4D2A05409012004B9062374B2A09905F909724079065
|
||||
S10BD61B508127029050818028
|
||||
S12386C4000000000000000000000000000000000000000000000030000000000000000062
|
||||
S11D86E44E00001E0005000000000000000000000000000000000000000007
|
||||
S12386FE000000000000000000000000000000000000000000000000000000000000000058
|
||||
S123871E00000000000000000000000000000000000000000000000000000026E20000002F
|
||||
S120873E0000000000000000007777772E6966697368372E636F6D000000000000D0
|
||||
S12380008200875B8200D6228200D6228200D6228200D6228200D6228200D6228200D622A2
|
||||
S12380208200D6228200D6228200D6228200D6228200D6228200D6228200D6228200D6226C
|
||||
S12380408200D6228200D6228200D6228200D6228200D6228200D6228200CEA48200CE6498
|
||||
S12380608200D6228200CFFA8200D6228200D6228200D6228200D6228200D6228200D6225B
|
||||
S11086B786C462000086FE640100875B003B
|
||||
S903FFFFFE
|
||||
@@ -0,0 +1,5 @@
|
||||
/* STM8S005K6.h */
|
||||
#ifdef MCU_NAME
|
||||
#define STM8S005K6 1
|
||||
#endif
|
||||
#include "STM8S105K.h"
|
||||
@@ -0,0 +1,786 @@
|
||||
/* STM8S105K.h */
|
||||
|
||||
/* Copyright (c) 2003-2012 STMicroelectronics */
|
||||
|
||||
#ifndef __STM8S105K__
|
||||
#define __STM8S105K__
|
||||
|
||||
/* STM8S105K */
|
||||
|
||||
/* Check MCU name */
|
||||
#ifdef MCU_NAME
|
||||
#define STM8S105K 1
|
||||
#if (MCU_NAME != STM8S105K)
|
||||
#error "wrong include file STM8S105K.h for chosen MCU!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __CSMC__
|
||||
#define DEF_8BIT_REG_AT(NAME,ADDRESS) volatile unsigned char NAME @ADDRESS
|
||||
#define DEF_16BIT_REG_AT(NAME,ADDRESS) volatile unsigned int NAME @ADDRESS
|
||||
#endif
|
||||
|
||||
#ifdef __RAISONANCE__
|
||||
#define DEF_8BIT_REG_AT(NAME,ADDRESS) at ADDRESS hreg NAME
|
||||
#define DEF_16BIT_REG_AT(NAME,ADDRESS) at ADDRESS hreg16 NAME
|
||||
#endif
|
||||
|
||||
/* Port A */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port A data output latch register */
|
||||
DEF_8BIT_REG_AT(PA_ODR,0x5000);
|
||||
|
||||
/* Port A input pin value register */
|
||||
DEF_8BIT_REG_AT(PA_IDR,0x5001);
|
||||
|
||||
/* Port A data direction register */
|
||||
DEF_8BIT_REG_AT(PA_DDR,0x5002);
|
||||
|
||||
/* Port A control register 1 */
|
||||
DEF_8BIT_REG_AT(PA_CR1,0x5003);
|
||||
|
||||
/* Port A control register 2 */
|
||||
DEF_8BIT_REG_AT(PA_CR2,0x5004);
|
||||
|
||||
/* Port B */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port B data output latch register */
|
||||
DEF_8BIT_REG_AT(PB_ODR,0x5005);
|
||||
|
||||
/* Port B input pin value register */
|
||||
DEF_8BIT_REG_AT(PB_IDR,0x5006);
|
||||
|
||||
/* Port B data direction register */
|
||||
DEF_8BIT_REG_AT(PB_DDR,0x5007);
|
||||
|
||||
/* Port B control register 1 */
|
||||
DEF_8BIT_REG_AT(PB_CR1,0x5008);
|
||||
|
||||
/* Port B control register 2 */
|
||||
DEF_8BIT_REG_AT(PB_CR2,0x5009);
|
||||
|
||||
/* Port C */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port C data output latch register */
|
||||
DEF_8BIT_REG_AT(PC_ODR,0x500a);
|
||||
|
||||
/* Port C input pin value register */
|
||||
DEF_8BIT_REG_AT(PC_IDR,0x500b);
|
||||
|
||||
/* Port C data direction register */
|
||||
DEF_8BIT_REG_AT(PC_DDR,0x500c);
|
||||
|
||||
/* Port C control register 1 */
|
||||
DEF_8BIT_REG_AT(PC_CR1,0x500d);
|
||||
|
||||
/* Port C control register 2 */
|
||||
DEF_8BIT_REG_AT(PC_CR2,0x500e);
|
||||
|
||||
/* Port D */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port D data output latch register */
|
||||
DEF_8BIT_REG_AT(PD_ODR,0x500f);
|
||||
|
||||
/* Port D input pin value register */
|
||||
DEF_8BIT_REG_AT(PD_IDR,0x5010);
|
||||
|
||||
/* Port D data direction register */
|
||||
DEF_8BIT_REG_AT(PD_DDR,0x5011);
|
||||
|
||||
/* Port D control register 1 */
|
||||
DEF_8BIT_REG_AT(PD_CR1,0x5012);
|
||||
|
||||
/* Port D control register 2 */
|
||||
DEF_8BIT_REG_AT(PD_CR2,0x5013);
|
||||
|
||||
/* Port E */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port E data output latch register */
|
||||
DEF_8BIT_REG_AT(PE_ODR,0x5014);
|
||||
|
||||
/* Port E input pin value register */
|
||||
DEF_8BIT_REG_AT(PE_IDR,0x5015);
|
||||
|
||||
/* Port E data direction register */
|
||||
DEF_8BIT_REG_AT(PE_DDR,0x5016);
|
||||
|
||||
/* Port E control register 1 */
|
||||
DEF_8BIT_REG_AT(PE_CR1,0x5017);
|
||||
|
||||
/* Port E control register 2 */
|
||||
DEF_8BIT_REG_AT(PE_CR2,0x5018);
|
||||
|
||||
/* Port F */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Port F data output latch register */
|
||||
DEF_8BIT_REG_AT(PF_ODR,0x5019);
|
||||
|
||||
/* Port F input pin value register */
|
||||
DEF_8BIT_REG_AT(PF_IDR,0x501a);
|
||||
|
||||
/* Port F data direction register */
|
||||
DEF_8BIT_REG_AT(PF_DDR,0x501b);
|
||||
|
||||
/* Port F control register 1 */
|
||||
DEF_8BIT_REG_AT(PF_CR1,0x501c);
|
||||
|
||||
/* Port F control register 2 */
|
||||
DEF_8BIT_REG_AT(PF_CR2,0x501d);
|
||||
|
||||
/* Flash */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Flash control register 1 */
|
||||
DEF_8BIT_REG_AT(FLASH_CR1,0x505a);
|
||||
|
||||
/* Flash control register 2 */
|
||||
DEF_8BIT_REG_AT(FLASH_CR2,0x505b);
|
||||
|
||||
/* Flash complementary control register 2 */
|
||||
DEF_8BIT_REG_AT(FLASH_NCR2,0x505c);
|
||||
|
||||
/* Flash protection register */
|
||||
DEF_8BIT_REG_AT(FLASH_FPR,0x505d);
|
||||
|
||||
/* Flash complementary protection register */
|
||||
DEF_8BIT_REG_AT(FLASH_NFPR,0x505e);
|
||||
|
||||
/* Flash in-application programming status register */
|
||||
DEF_8BIT_REG_AT(FLASH_IAPSR,0x505f);
|
||||
|
||||
/* Flash Program memory unprotection register */
|
||||
DEF_8BIT_REG_AT(FLASH_PUKR,0x5062);
|
||||
|
||||
/* Data EEPROM unprotection register */
|
||||
DEF_8BIT_REG_AT(FLASH_DUKR,0x5064);
|
||||
|
||||
/* External Interrupt Control Register (ITC) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* External interrupt control register 1 */
|
||||
DEF_8BIT_REG_AT(EXTI_CR1,0x50a0);
|
||||
|
||||
/* External interrupt control register 2 */
|
||||
DEF_8BIT_REG_AT(EXTI_CR2,0x50a1);
|
||||
|
||||
/* Reset (RST) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Reset status register 1 */
|
||||
DEF_8BIT_REG_AT(RST_SR,0x50b3);
|
||||
|
||||
/* Clock Control (CLK) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Internal clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_ICKR,0x50c0);
|
||||
|
||||
/* External clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_ECKR,0x50c1);
|
||||
|
||||
/* Clock master status register */
|
||||
DEF_8BIT_REG_AT(CLK_CMSR,0x50c3);
|
||||
|
||||
/* Clock master switch register */
|
||||
DEF_8BIT_REG_AT(CLK_SWR,0x50c4);
|
||||
|
||||
/* Clock switch control register */
|
||||
DEF_8BIT_REG_AT(CLK_SWCR,0x50c5);
|
||||
|
||||
/* Clock divider register */
|
||||
DEF_8BIT_REG_AT(CLK_CKDIVR,0x50c6);
|
||||
|
||||
/* Peripheral clock gating register 1 */
|
||||
DEF_8BIT_REG_AT(CLK_PCKENR1,0x50c7);
|
||||
|
||||
/* Clock security system register */
|
||||
DEF_8BIT_REG_AT(CLK_CSSR,0x50c8);
|
||||
|
||||
/* Configurable clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_CCOR,0x50c9);
|
||||
|
||||
/* Peripheral clock gating register 2 */
|
||||
DEF_8BIT_REG_AT(CLK_PCKENR2,0x50ca);
|
||||
|
||||
/* CAN clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_CANCCR,0x50cb);
|
||||
|
||||
/* HSI clock calibration trimming register */
|
||||
DEF_8BIT_REG_AT(CLK_HSITRIMR,0x50cc);
|
||||
|
||||
/* SWIM clock control register */
|
||||
DEF_8BIT_REG_AT(CLK_SWIMCCR,0x50cd);
|
||||
|
||||
/* Window Watchdog (WWDG) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* WWDG Control Register */
|
||||
DEF_8BIT_REG_AT(WWDG_CR,0x50d1);
|
||||
|
||||
/* WWDR Window Register */
|
||||
DEF_8BIT_REG_AT(WWDG_WR,0x50d2);
|
||||
|
||||
/* Independent Watchdog (IWDG) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* IWDG Key Register */
|
||||
DEF_8BIT_REG_AT(IWDG_KR,0x50e0);
|
||||
|
||||
/* IWDG Prescaler Register */
|
||||
DEF_8BIT_REG_AT(IWDG_PR,0x50e1);
|
||||
|
||||
/* IWDG Reload Register */
|
||||
DEF_8BIT_REG_AT(IWDG_RLR,0x50e2);
|
||||
|
||||
/* Auto Wake-Up (AWU) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* AWU Control/Status Register */
|
||||
DEF_8BIT_REG_AT(AWU_CSR,0x50f0);
|
||||
|
||||
/* AWU asynchronous prescaler buffer register */
|
||||
DEF_8BIT_REG_AT(AWU_APR,0x50f1);
|
||||
|
||||
/* AWU Timebase selection register */
|
||||
DEF_8BIT_REG_AT(AWU_TBR,0x50f2);
|
||||
|
||||
/* Beeper (BEEP) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* BEEP Control/Status Register */
|
||||
DEF_8BIT_REG_AT(BEEP_CSR,0x50f3);
|
||||
|
||||
/* Serial Peripheral Interface (SPI) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
DEF_8BIT_REG_AT(SPI_CR1,0x5200);
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
DEF_8BIT_REG_AT(SPI_CR2,0x5201);
|
||||
|
||||
/* SPI Interrupt Control Register */
|
||||
DEF_8BIT_REG_AT(SPI_ICR,0x5202);
|
||||
|
||||
/* SPI Status Register */
|
||||
DEF_8BIT_REG_AT(SPI_SR,0x5203);
|
||||
|
||||
/* SPI Data Register */
|
||||
DEF_8BIT_REG_AT(SPI_DR,0x5204);
|
||||
|
||||
/* SPI CRC Polynomial Register */
|
||||
DEF_8BIT_REG_AT(SPI_CRCPR,0x5205);
|
||||
|
||||
/* SPI Rx CRC Register */
|
||||
DEF_8BIT_REG_AT(SPI_RXCRCR,0x5206);
|
||||
|
||||
/* SPI Tx CRC Register */
|
||||
DEF_8BIT_REG_AT(SPI_TXCRCR,0x5207);
|
||||
|
||||
/* I2C Bus Interface (I2C) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* I2C control register 1 */
|
||||
DEF_8BIT_REG_AT(I2C_CR1,0x5210);
|
||||
|
||||
/* I2C control register 2 */
|
||||
DEF_8BIT_REG_AT(I2C_CR2,0x5211);
|
||||
|
||||
/* I2C frequency register */
|
||||
DEF_8BIT_REG_AT(I2C_FREQR,0x5212);
|
||||
|
||||
/* I2C Own address register low */
|
||||
DEF_8BIT_REG_AT(I2C_OARL,0x5213);
|
||||
|
||||
/* I2C Own address register high */
|
||||
DEF_8BIT_REG_AT(I2C_OARH,0x5214);
|
||||
|
||||
/* I2C data register */
|
||||
DEF_8BIT_REG_AT(I2C_DR,0x5216);
|
||||
|
||||
/* I2C status register 1 */
|
||||
DEF_8BIT_REG_AT(I2C_SR1,0x5217);
|
||||
|
||||
/* I2C status register 2 */
|
||||
DEF_8BIT_REG_AT(I2C_SR2,0x5218);
|
||||
|
||||
/* I2C status register 3 */
|
||||
DEF_8BIT_REG_AT(I2C_SR3,0x5219);
|
||||
|
||||
/* I2C interrupt control register */
|
||||
DEF_8BIT_REG_AT(I2C_ITR,0x521a);
|
||||
|
||||
/* I2C Clock control register low */
|
||||
DEF_8BIT_REG_AT(I2C_CCRL,0x521b);
|
||||
|
||||
/* I2C Clock control register high */
|
||||
DEF_8BIT_REG_AT(I2C_CCRH,0x521c);
|
||||
|
||||
/* I2C TRISE register */
|
||||
DEF_8BIT_REG_AT(I2C_TRISER,0x521d);
|
||||
|
||||
/* I2C packet error checking register */
|
||||
DEF_8BIT_REG_AT(I2C_PECR,0x521e);
|
||||
|
||||
/* LIN Universal asynch. receiver transmitter (UART2) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* UART2 Status Register */
|
||||
DEF_8BIT_REG_AT(UART2_SR,0x5240);
|
||||
|
||||
/* UART2 Data Register */
|
||||
DEF_8BIT_REG_AT(UART2_DR,0x5241);
|
||||
|
||||
/* UART2 Baud Rate Register 1 */
|
||||
DEF_8BIT_REG_AT(UART2_BRR1,0x5242);
|
||||
|
||||
/* UART2 Baud Rate Register 2 */
|
||||
DEF_8BIT_REG_AT(UART2_BRR2,0x5243);
|
||||
|
||||
/* UART2 Control Register 1 */
|
||||
DEF_8BIT_REG_AT(UART2_CR1,0x5244);
|
||||
|
||||
/* UART2 Control Register 2 */
|
||||
DEF_8BIT_REG_AT(UART2_CR2,0x5245);
|
||||
|
||||
/* UART2 Control Register 3 */
|
||||
DEF_8BIT_REG_AT(UART2_CR3,0x5246);
|
||||
|
||||
/* UART2 Control Register 4 */
|
||||
DEF_8BIT_REG_AT(UART2_CR4,0x5247);
|
||||
|
||||
/* UART2 Control Register 5 */
|
||||
DEF_8BIT_REG_AT(UART2_CR5,0x5248);
|
||||
|
||||
/* UART2 Control Register 6 */
|
||||
DEF_8BIT_REG_AT(UART2_CR6,0x5249);
|
||||
|
||||
/* UART2 Guard time Register */
|
||||
DEF_8BIT_REG_AT(UART2_GTR,0x524a);
|
||||
|
||||
/* UART2 Prescaler Register */
|
||||
DEF_8BIT_REG_AT(UART2_PSCR,0x524b);
|
||||
|
||||
/* 16-Bit Timer 1 (TIM1) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM1 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_CR1,0x5250);
|
||||
|
||||
/* TIM1 Control register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_CR2,0x5251);
|
||||
|
||||
/* TIM1 Slave Mode Control register */
|
||||
DEF_8BIT_REG_AT(TIM1_SMCR,0x5252);
|
||||
|
||||
/* TIM1 external trigger register */
|
||||
DEF_8BIT_REG_AT(TIM1_ETR,0x5253);
|
||||
|
||||
/* TIM1 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM1_IER,0x5254);
|
||||
|
||||
/* TIM1 Status register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_SR1,0x5255);
|
||||
|
||||
/* TIM1 Status register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_SR2,0x5256);
|
||||
|
||||
/* TIM1 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM1_EGR,0x5257);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR1,0x5258);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR2,0x5259);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 3 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR3,0x525a);
|
||||
|
||||
/* TIM1 Capture/Compare mode register 4 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCMR4,0x525b);
|
||||
|
||||
/* TIM1 Capture/Compare enable register 1 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCER1,0x525c);
|
||||
|
||||
/* TIM1 Capture/Compare enable register 2 */
|
||||
DEF_8BIT_REG_AT(TIM1_CCER2,0x525d);
|
||||
|
||||
/* TIM1 Counter */
|
||||
DEF_16BIT_REG_AT(TIM1_CNTR,0x525e);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CNTRH,0x525e);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CNTRL,0x525f);
|
||||
|
||||
/* TIM1 Prescaler register */
|
||||
DEF_16BIT_REG_AT(TIM1_PSCR,0x5260);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_PSCRH,0x5260);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_PSCRL,0x5261);
|
||||
|
||||
/* TIM1 Auto-reload register */
|
||||
DEF_16BIT_REG_AT(TIM1_ARR,0x5262);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_ARRH,0x5262);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_ARRL,0x5263);
|
||||
|
||||
/* TIM1 Repetition counter register */
|
||||
DEF_8BIT_REG_AT(TIM1_RCR,0x5264);
|
||||
|
||||
/* TIM1 Capture/Compare register 1 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR1,0x5265);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR1H,0x5265);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR1L,0x5266);
|
||||
|
||||
/* TIM1 Capture/Compare register 2 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR2,0x5267);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR2H,0x5267);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR2L,0x5268);
|
||||
|
||||
/* TIM1 Capture/Compare register 3 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR3,0x5269);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR3H,0x5269);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR3L,0x526a);
|
||||
|
||||
/* TIM1 Capture/Compare register 4 */
|
||||
DEF_16BIT_REG_AT(TIM1_CCR4,0x526b);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR4H,0x526b);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM1_CCR4L,0x526c);
|
||||
|
||||
/* TIM1 Break register */
|
||||
DEF_8BIT_REG_AT(TIM1_BKR,0x526d);
|
||||
|
||||
/* TIM1 Dead-time register */
|
||||
DEF_8BIT_REG_AT(TIM1_DTR,0x526e);
|
||||
|
||||
/* TIM1 Output idle state register */
|
||||
DEF_8BIT_REG_AT(TIM1_OISR,0x526f);
|
||||
|
||||
/* 16-Bit Timer 2 (TIM2) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM2 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_CR1,0x5300);
|
||||
|
||||
/* TIM2 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM2_IER,0x5301);
|
||||
|
||||
/* TIM2 Status register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_SR1,0x5302);
|
||||
|
||||
/* TIM2 Status register 2 */
|
||||
DEF_8BIT_REG_AT(TIM2_SR2,0x5303);
|
||||
|
||||
/* TIM2 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM2_EGR,0x5304);
|
||||
|
||||
/* TIM2 Capture/Compare mode register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCMR1,0x5305);
|
||||
|
||||
/* TIM2 Capture/Compare mode register 2 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCMR2,0x5306);
|
||||
|
||||
/* TIM2 Capture/Compare mode register 3 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCMR3,0x5307);
|
||||
|
||||
/* TIM2 Capture/Compare enable register 1 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCER1,0x5308);
|
||||
|
||||
/* TIM2 Capture/Compare enable register 2 */
|
||||
DEF_8BIT_REG_AT(TIM2_CCER2,0x5309);
|
||||
|
||||
/* TIM2 Counter */
|
||||
DEF_16BIT_REG_AT(TIM2_CNTR,0x530a);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CNTRH,0x530a);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CNTRL,0x530b);
|
||||
|
||||
/* TIM2 Prescaler register */
|
||||
DEF_8BIT_REG_AT(TIM2_PSCR,0x530c);
|
||||
|
||||
/* TIM2 Auto-reload register */
|
||||
DEF_16BIT_REG_AT(TIM2_ARR,0x530d);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_ARRH,0x530d);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_ARRL,0x530e);
|
||||
|
||||
/* TIM2 Capture/Compare register 1 */
|
||||
DEF_16BIT_REG_AT(TIM2_CCR1,0x530f);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR1H,0x530f);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR1L,0x5310);
|
||||
|
||||
/* TIM2 Capture/Compare register 2 */
|
||||
DEF_16BIT_REG_AT(TIM2_CCR2,0x5311);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR2H,0x5311);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR2L,0x5312);
|
||||
|
||||
/* TIM2 Capture/Compare register 3 */
|
||||
DEF_16BIT_REG_AT(TIM2_CCR3,0x5313);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR3H,0x5313);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM2_CCR3L,0x5314);
|
||||
|
||||
/* 16-Bit Timer 3 (TIM3) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM3 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_CR1,0x5320);
|
||||
|
||||
/* TIM3 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM3_IER,0x5321);
|
||||
|
||||
/* TIM3 Status register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_SR1,0x5322);
|
||||
|
||||
/* TIM3 Status register 2 */
|
||||
DEF_8BIT_REG_AT(TIM3_SR2,0x5323);
|
||||
|
||||
/* TIM3 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM3_EGR,0x5324);
|
||||
|
||||
/* TIM3 Capture/Compare mode register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_CCMR1,0x5325);
|
||||
|
||||
/* TIM3 Capture/Compare mode register 2 */
|
||||
DEF_8BIT_REG_AT(TIM3_CCMR2,0x5326);
|
||||
|
||||
/* TIM3 Capture/Compare enable register 1 */
|
||||
DEF_8BIT_REG_AT(TIM3_CCER1,0x5327);
|
||||
|
||||
/* TIM3 Counter */
|
||||
DEF_16BIT_REG_AT(TIM3_CNTR,0x5328);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_CNTRH,0x5328);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_CNTRL,0x5329);
|
||||
|
||||
/* TIM3 Prescaler register */
|
||||
DEF_8BIT_REG_AT(TIM3_PSCR,0x532a);
|
||||
|
||||
/* TIM3 Auto-reload register */
|
||||
DEF_16BIT_REG_AT(TIM3_ARR,0x532b);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_ARRH,0x532b);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_ARRL,0x532c);
|
||||
|
||||
/* TIM3 Capture/Compare register */
|
||||
DEF_16BIT_REG_AT(TIM3_CCR1,0x532d);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR1H,0x532d);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR1L,0x532e);
|
||||
|
||||
/* TIM3 Capture/Compare register */
|
||||
DEF_16BIT_REG_AT(TIM3_CCR2,0x532f);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR2H,0x532f);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(TIM3_CCR2L,0x5330);
|
||||
|
||||
/* 8-Bit Timer 4 (TIM4) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* TIM4 Control register 1 */
|
||||
DEF_8BIT_REG_AT(TIM4_CR1,0x5340);
|
||||
|
||||
/* TIM4 Interrupt enable register */
|
||||
DEF_8BIT_REG_AT(TIM4_IER,0x5341);
|
||||
|
||||
/* TIM4 Status register */
|
||||
DEF_8BIT_REG_AT(TIM4_SR,0x5342);
|
||||
|
||||
/* TIM4 Event Generation register */
|
||||
DEF_8BIT_REG_AT(TIM4_EGR,0x5343);
|
||||
|
||||
/* TIM4 Counter */
|
||||
DEF_8BIT_REG_AT(TIM4_CNTR,0x5344);
|
||||
|
||||
/* TIM4 Prescaler register */
|
||||
DEF_8BIT_REG_AT(TIM4_PSCR,0x5345);
|
||||
|
||||
/* TIM4 Auto-reload register */
|
||||
DEF_8BIT_REG_AT(TIM4_ARR,0x5346);
|
||||
|
||||
/* 10-Bit A/D Converter (ADC1) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* ADC Data buffer Register 0 */
|
||||
DEF_16BIT_REG_AT(ADC_DB0R,0x53e0);
|
||||
/* Data Buffer register 0 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB0RH,0x53e0);
|
||||
/* Data Buffer register 0 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB0RL,0x53e1);
|
||||
|
||||
/* ADC Data buffer Register 1 */
|
||||
DEF_16BIT_REG_AT(ADC_DB1R,0x53e2);
|
||||
/* Data Buffer register 1 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB1RH,0x53e2);
|
||||
/* Data Buffer register 1 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB1RL,0x53e3);
|
||||
|
||||
/* ADC Data buffer Register 2 */
|
||||
DEF_16BIT_REG_AT(ADC_DB2R,0x53e4);
|
||||
/* Data Buffer register 2 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB2RH,0x53e4);
|
||||
/* Data Buffer register 2 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB2RL,0x53e5);
|
||||
|
||||
/* ADC Data buffer Register 3 */
|
||||
DEF_16BIT_REG_AT(ADC_DB3R,0x53e6);
|
||||
/* Data Buffer register 3 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB3RH,0x53e6);
|
||||
/* Data Buffer register 3 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB3RL,0x53e7);
|
||||
|
||||
/* ADC Data buffer Register 4 */
|
||||
DEF_16BIT_REG_AT(ADC_DB4R,0x53e8);
|
||||
/* Data Buffer register 4 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB4RH,0x53e8);
|
||||
/* Data Buffer register 4 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB4RL,0x53e9);
|
||||
|
||||
/* ADC Data buffer Register 5 */
|
||||
DEF_16BIT_REG_AT(ADC_DB5R,0x53ea);
|
||||
/* Data Buffer register 5 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB5RH,0x53ea);
|
||||
/* Data Buffer register 5 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB5RL,0x53eb);
|
||||
|
||||
/* ADC Data buffer Register 6 */
|
||||
DEF_16BIT_REG_AT(ADC_DB6R,0x53ec);
|
||||
/* Data Buffer register 6 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB6RH,0x53ec);
|
||||
/* Data Buffer register 6 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB6RL,0x53ed);
|
||||
|
||||
/* ADC Data buffer Register 7 */
|
||||
DEF_16BIT_REG_AT(ADC_DB7R,0x53ee);
|
||||
/* Data Buffer register 7 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB7RH,0x53ee);
|
||||
/* Data Buffer register 7 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB7RL,0x53ef);
|
||||
|
||||
/* ADC Data buffer Register 8 */
|
||||
DEF_16BIT_REG_AT(ADC_DB8R,0x53f0);
|
||||
/* Data Buffer register 8 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB8RH,0x53f0);
|
||||
/* Data Buffer register 8 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB8RL,0x53f1);
|
||||
|
||||
/* ADC Data buffer Register 9 */
|
||||
DEF_16BIT_REG_AT(ADC_DB9R,0x53f2);
|
||||
/* Data Buffer register 9 High */
|
||||
DEF_8BIT_REG_AT(ADC_DB9RH,0x53f2);
|
||||
/* Data Buffer register 9 Low */
|
||||
DEF_8BIT_REG_AT(ADC_DB9RL,0x53f3);
|
||||
|
||||
/* ADC Control/Status Register */
|
||||
DEF_8BIT_REG_AT(ADC_CSR,0x5400);
|
||||
|
||||
/* ADC Configuration Register 1 */
|
||||
DEF_8BIT_REG_AT(ADC_CR1,0x5401);
|
||||
|
||||
/* ADC Configuration Register 2 */
|
||||
DEF_8BIT_REG_AT(ADC_CR2,0x5402);
|
||||
|
||||
/* ADC Configuration Register 3 */
|
||||
DEF_8BIT_REG_AT(ADC_CR3,0x5403);
|
||||
|
||||
/* ADC Data Register */
|
||||
DEF_16BIT_REG_AT(ADC_DR,0x5404);
|
||||
/* Data bits High */
|
||||
DEF_8BIT_REG_AT(ADC_DRH,0x5404);
|
||||
/* Data bits Low */
|
||||
DEF_8BIT_REG_AT(ADC_DRL,0x5405);
|
||||
|
||||
/* ADC Schmitt Trigger Disable Register */
|
||||
DEF_16BIT_REG_AT(ADC_TDR,0x5406);
|
||||
/* Schmitt trigger disable High */
|
||||
DEF_8BIT_REG_AT(ADC_TDRH,0x5406);
|
||||
/* Schmitt trigger disable Low */
|
||||
DEF_8BIT_REG_AT(ADC_TDRL,0x5407);
|
||||
|
||||
/* ADC High Threshold Register */
|
||||
DEF_16BIT_REG_AT(ADC_HTR,0x5408);
|
||||
/* High Threshold Register High */
|
||||
DEF_8BIT_REG_AT(ADC_HTRH,0x5408);
|
||||
/* High Threshold Register Low */
|
||||
DEF_8BIT_REG_AT(ADC_HTRL,0x5409);
|
||||
|
||||
/* ADC Low Threshold Register */
|
||||
DEF_16BIT_REG_AT(ADC_LTR,0x540a);
|
||||
/* Low Threshold Register High */
|
||||
DEF_8BIT_REG_AT(ADC_LTRH,0x540a);
|
||||
/* Low Threshold Register Low */
|
||||
DEF_8BIT_REG_AT(ADC_LTRL,0x540b);
|
||||
|
||||
/* ADC Analog Watchdog Status Register */
|
||||
DEF_16BIT_REG_AT(ADC_AWSR,0x540c);
|
||||
/* Analog Watchdog Status register High */
|
||||
DEF_8BIT_REG_AT(ADC_AWSRH,0x540c);
|
||||
/* Analog Watchdog Status register Low */
|
||||
DEF_8BIT_REG_AT(ADC_AWSRL,0x540d);
|
||||
|
||||
/* ADC Analog Watchdog Control Register */
|
||||
DEF_16BIT_REG_AT(ADC_AWCR,0x540e);
|
||||
/* Analog Watchdog Control register High */
|
||||
DEF_8BIT_REG_AT(ADC_AWCRH,0x540e);
|
||||
/* Analog Watchdog Control register Low */
|
||||
DEF_8BIT_REG_AT(ADC_AWCRL,0x540f);
|
||||
|
||||
/* Global configuration register (CFG) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* CFG Global configuration register */
|
||||
DEF_8BIT_REG_AT(CFG_GCR,0x7f60);
|
||||
|
||||
/* Interrupt Software Priority Register (ITC) */
|
||||
/*****************************************************************/
|
||||
|
||||
/* Interrupt Software priority register 1 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR1,0x7f70);
|
||||
|
||||
/* Interrupt Software priority register 2 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR2,0x7f71);
|
||||
|
||||
/* Interrupt Software priority register 3 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR3,0x7f72);
|
||||
|
||||
/* Interrupt Software priority register 4 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR4,0x7f73);
|
||||
|
||||
/* Interrupt Software priority register 5 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR5,0x7f74);
|
||||
|
||||
/* Interrupt Software priority register 6 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR6,0x7f75);
|
||||
|
||||
/* Interrupt Software priority register 7 */
|
||||
DEF_8BIT_REG_AT(ITC_SPR7,0x7f76);
|
||||
|
||||
#endif /* __STM8S105K__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,63 @@
|
||||
/* BASIC INTERRUPT VECTOR TABLE FOR STM8 devices
|
||||
* Copyright (c) 2007 STMicroelectronics
|
||||
*/
|
||||
|
||||
typedef void @far (*interrupt_handler_t)(void);
|
||||
|
||||
struct interrupt_vector {
|
||||
unsigned char interrupt_instruction;
|
||||
interrupt_handler_t interrupt_handler;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
@far @interrupt void NonHandledInterrupt (void)
|
||||
{
|
||||
// in order to detect unexpected events during development,
|
||||
// it is recommended to set a breakpoint on the following instruction
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void _stext(); /* startup routine */
|
||||
extern @far @interrupt void TIM4_UPD_OVF_IRQHandler (void);
|
||||
extern @far @interrupt void UART2_Send_IRQHandler (void);
|
||||
extern @far @interrupt void UART2_Recv_IRQHandler (void);
|
||||
|
||||
struct interrupt_vector const _vectab[] = {
|
||||
{0x82, (interrupt_handler_t)_stext}, /* reset */
|
||||
{0x82, NonHandledInterrupt}, /* trap */
|
||||
{0x82, NonHandledInterrupt}, /* irq0 */
|
||||
{0x82, NonHandledInterrupt}, /* irq1 */
|
||||
{0x82, NonHandledInterrupt}, /* irq2 */
|
||||
{0x82, NonHandledInterrupt}, /* irq3 */
|
||||
{0x82, NonHandledInterrupt}, /* irq4 */
|
||||
{0x82, NonHandledInterrupt}, /* irq5 */
|
||||
{0x82, NonHandledInterrupt}, /* irq6 */
|
||||
{0x82, NonHandledInterrupt}, /* irq7 */
|
||||
{0x82, NonHandledInterrupt}, /* irq8 */
|
||||
{0x82, NonHandledInterrupt}, /* irq9 */
|
||||
{0x82, NonHandledInterrupt}, /* irq10 */
|
||||
{0x82, NonHandledInterrupt}, /* irq11 */
|
||||
{0x82, NonHandledInterrupt}, /* irq12 */
|
||||
{0x82, NonHandledInterrupt}, /* irq13 */
|
||||
{0x82, NonHandledInterrupt}, /* irq14 */
|
||||
{0x82, NonHandledInterrupt}, /* irq15 */
|
||||
{0x82, NonHandledInterrupt}, /* irq16 */
|
||||
{0x82, NonHandledInterrupt}, /* irq17 */
|
||||
{0x82, NonHandledInterrupt}, /* irq18 */
|
||||
{0x82, NonHandledInterrupt}, /* irq19 */
|
||||
{0x82, UART2_Send_IRQHandler}, /* irq20 UART2/3·¢ËÍÖжÏ*/
|
||||
{0x82, UART2_Recv_IRQHandler}, /* irq21 UART2/3½ÓÊÕÖжÏ*/
|
||||
{0x82, NonHandledInterrupt}, /* irq22 */
|
||||
{0x82, TIM4_UPD_OVF_IRQHandler}, /* irq23 */
|
||||
{0x82, NonHandledInterrupt}, /* irq24 */
|
||||
{0x82, NonHandledInterrupt}, /* irq25 */
|
||||
{0x82, NonHandledInterrupt}, /* irq26 */
|
||||
{0x82, NonHandledInterrupt}, /* irq27 */
|
||||
{0x82, NonHandledInterrupt}, /* irq28 */
|
||||
{0x82, NonHandledInterrupt}, /* irq29 */
|
||||
};
|
||||
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||||
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|
||||
S12388AC1E017B0543E403E7038581725F50A0725F50A181899E4D27149EA101270F9EA187
|
||||
S12388CC02270A9EA10327059EA10426034F2010AE004489AE000089AE80FCCD84855B04EB
|
||||
S12388EC0D0227127B02A101270C7B02A10227067B02A10326034F2010AE004589AE00008E
|
||||
S123890C89AE80FCCD84855B047B014D270E4A271D4A272E4A27424A27562064C650A0A4DC
|
||||
S123892CFCC750A0C650A01A02C750A02052C650A0A4F3C750A07B024848CA50A0C750A0F7
|
||||
S123894C203EC650A0A4CFC750A07B0297A610429FCA50A0C750A02027C650A0A43FC750B6
|
||||
S123896CA07B0297A640429FCA50A0C750A02010C650A1A4FCC750A1C650A11A02C750A131
|
||||
S123898C8581884D2704A10426034F2010AE006D89AE000089AE80FCCD84855B0472155063
|
||||
S12389ACA1C650A11A01C750A1848188880F014D2710A101270CA1022708A1032704A104B8
|
||||
S12389CC26034F2010AE007E89AE000089AE80FCCD84855B047B024D270E4A27144A271C83
|
||||
S12389EC4A27254A27302035C650A0A4036B01202CC650A0A40C44446B012021C650A0A4D1
|
||||
S1238A0C304EA40F6B012015C650A0A4C04E4444A4036B012007C650A1A4036B017B01857F
|
||||
S1138A2C81880F01C650A1A4046B017B015B0181F9
|
||||
S10D81420000000006000000FA002F
|
||||
S12380008200814C82008198820081998200819A8200819B8200819C8200819D820081A6B3
|
||||
S1238020820081B1820081B28200819782008197820081B3820081B4820081B5820081B6C1
|
||||
S1238040820081B78200819782008197820081B8820081B9820081BA8200819782008197C6
|
||||
S1238060820081BB820081BC820081F082008197820081978200819782008197820081978A
|
||||
S10B813A8142620000814C0047
|
||||
S903FFFFFE
|
||||
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@@ -0,0 +1,18 @@
|
||||
if [ "$1" = "quartzPro5" ]; then
|
||||
echo "stop quartzPro5......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/quartzPro5/shutdown.sh
|
||||
elif [ "$1" = "ifish6" ]; then
|
||||
echo "stop ifish6......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish6/shutdown.sh
|
||||
elif [ "$1" = "ifish7" ]; then
|
||||
echo "stop ifish7......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish7/shutdown.sh
|
||||
elif [ "$1" = "ifishSystem8" ]; then
|
||||
echo "stop ifishSystem8......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSystem8/shutdown.sh
|
||||
elif [ "$1" = "ifishSocket9" ]; then
|
||||
echo "stop ifishSocket9......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSocket9/shutdown.sh
|
||||
else
|
||||
echo "parameter error"
|
||||
fi
|
||||
@@ -0,0 +1,28 @@
|
||||
if [ "$1" = "quartzPro5" ]; then
|
||||
echo "rmove quartzPro5 war package......"
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/quartzPro5/webapps/quartzPro.war
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/quartzPro5/app/*
|
||||
cp ../package/quartzPro.war /usr/local/apache-tomcat-7.0.64/tomcat-instance/quartzPro5/webapps/
|
||||
elif [ "$1" = "ifish6" ]; then
|
||||
echo "rmove ifish6 war package......"
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish6/webapps/ifish.war
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish6/app/*
|
||||
cp ../package/ifish.war /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish6/webapps/
|
||||
elif [ "$1" = "ifish7" ]; then
|
||||
echo "rmove ifish7 war package......"
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish7/webapps/ifish.war
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish7/app/*
|
||||
cp ../package/ifish.war /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish7/webapps/
|
||||
elif [ "$1" = "ifishSystem8" ]; then
|
||||
echo "rmove ifishSystem8 war package......"
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSystem8/webapps/ifishSystem.war
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSystem8/app/*
|
||||
cp ../package/ifishSystem.war /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSystem8/webapps/
|
||||
elif [ "$1" = "ifishSocket9" ]; then
|
||||
echo "rmove ifishSocket9 war package......"
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSocket9/webapps/ifishSocket.war
|
||||
rm -rf /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSocket9/app/*
|
||||
cp ../package/ifishSocket.war /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSocket9/webapps/
|
||||
else
|
||||
echo "parameter error"
|
||||
fi
|
||||
@@ -0,0 +1,18 @@
|
||||
if [ "$1" = "quartzPro5" ]; then
|
||||
echo "quartzPro5 publish......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/quartzPro5/startup.sh
|
||||
elif [ "$1" = "ifish6" ]; then
|
||||
echo "ifish6 publish......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish6/startup.sh
|
||||
elif [ "$1" = "ifish7" ]; then
|
||||
echo "ifish7 publish......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifish7/startup.sh
|
||||
elif [ "$1" = "ifishSystem8" ]; then
|
||||
echo "ifishSystem8 publish......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSystem8/startup.sh
|
||||
elif [ "$1" = "ifishSocket9" ]; then
|
||||
echo "ifishSocket9 publish......"
|
||||
sh /usr/local/apache-tomcat-7.0.64/tomcat-instance/ifishSocket9/startup.sh
|
||||
else
|
||||
echo "parameter error"
|
||||
fi
|
||||
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@@ -0,0 +1,19 @@
|
||||
下面为工具项目
|
||||
|
||||
1.在本地后台 设备管理—设备类型 中添加设备类型
|
||||
|
||||
2.在本地后台 厂家管理—电子厂信息—修改对应厂家的硬件类型，勾上刚才添加的设备类型
|
||||
|
||||
3.测试工具的 socket.js，搜索getFactoryInfo方法，并修改url为本地后台
|
||||
|
||||
4.添加字节数对象
|
||||
|
||||
5.在编码解码处将发送信息实例化为字节(为了避免错误，查看84字节睿芯独立，这个地方注释比较全，而且正确)
|
||||
|
||||
6.someServer处添加新设备的信息
|
||||
|
||||
7.如果有新的功能代码，在orderModel里进行添加，并在someServer的sendModel里进行添加方法
|
||||
|
||||
|
||||
下面为Socket服务器项目
|
||||
|
||||
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Reference in New Issue
Block a user